This project is read-only.

Introduction

The goal of the Groundhog project is to provide a simple and easy to use framework for accessing a SATA-based hard drive or solid-state drive from a Xilinx FPGA. The existing codebase is compatible with SATA I and SATA II and we include a simple testbench to get you familiar with the basic operation of Groundhog.

System Requirements

1)       The included project files target a Digilent XUP-V5 board. The codebase can be easily ported to other boards with a Virtex 5 LXT/SXT/TXT/FXT device.

2)       Xilinx ISE and a JTAG programming cable to create/compile user hardware-side applications and program the FPGA board (tested with ISE versions 13.2).

3)       The included testbench uses Simple Interface for Reconfigurable Computing (SIRC) library to communicate between a small test program running on a Windows PC and a simple example circuit attached to the Groundhog SATA controller on the FPGA. This is not needed to build your own Groundhog-based applications, but it is handy to prove that you have everything set up and working correctly before embarking on your own projects.

At minimum, to run the included testbench will require a Windows XP/Vista/7 PC, a network card capable of operating at 1Gbps, and an Ethernet crossover cable (or a gigabit Ethernet switch).

For convenience, we have redistributed some of the SIRC software and hardware source files, along with replicating some of the documentation in the README.  Keep in mind though, SIRC is an evolving codebase. If you would like to use SIRC in other projects, it is best to read the documentation and download a fresh copy of the latest source code from:

http://research.microsoft.com/en-us/downloads/d335458e-c241-4845-b0ef-c587c8d29796/.

Last edited Dec 5, 2013 at 9:25 AM by Kusanagi2012, version 19

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