VC709-released error in reset signal

The HBA reset signal is link_reset = soft_reset | hard_reset and it is the reset signal to the link.v The link.v module generates the reset signal to the transport.v - reset_from_link. This signal ...

Id #1050 | Release: None | Updated: Dec 18, 2014 at 3:47 PM by vruizescribano | Created: Dec 18, 2014 at 3:47 PM by vruizescribano

Constructor Failed with code -7

i have a xilinx ml505 xupv5-lx110t tried to load the system.bit file given in the download and tried to use example.exe. Have also connected the Ethernet cable, jtag, sata cable. every thing is d...

Id #995 | Release: None | Updated: Jul 7, 2014 at 3:42 PM by magicvinodh | Created: Jul 7, 2014 at 3:42 PM by magicvinodh

16 sectors in one DataFIS

According to comments in transport layer // Maximum size of any FIS is 8 KiB // Because the first DW (4 bytes) contains the FIS type (0x46) // we cannot put more than 15 sectors into a single Dat...

Id #920 | Release: None | Updated: Jan 13, 2014 at 12:53 PM by Kusanagi2012 | Created: Jan 13, 2014 at 6:56 AM by Dimidrol76

Go to SENDFIS_PAYLOAD_AHOLD1 when to_link_send_underrun

In SENDFIS_PAYLOAD state when device send us HOLDp and at the same time we have to_link_send_underrun == 1, Link FSM go to SENDFIS_PAYLOAD_AHOLD1 not correctly. In result transmitted data and scram...

Id #919 | Release: None | Updated: Jan 11, 2014 at 8:33 AM by Dimidrol76 | Created: Jan 11, 2014 at 8:29 AM by Dimidrol76

ALIGNp sending is divided in two stages

ALIGNp sending rule (every 512 WORD 2 consecutive primitives) not serviced correctly when device (SENDFIS_PAYLOAD_AHOLD3, SENDFIS_PAYLOAD_HOLD) to SENDFIS_PAYLOAD transitions occurs. As a result AL...

Id #918 | Release: None | Updated: Jan 10, 2014 at 2:01 PM by Dimidrol76 | Created: Jan 10, 2014 at 2:01 PM by Dimidrol76

Hangs in SENDFIS_PAYLOAD_HOLD

to_link_send_underrun may not to go low if UNDERRUNLIM is 3 and it is remains send just one DWORD. It results to freeze in SENDFIS_PAYLOAD_HOLD (Link) state.

Id #917 | Release: None | Updated: Jan 7, 2014 at 5:40 PM by Dimidrol76 | Created: Jan 7, 2014 at 5:40 PM by Dimidrol76

OCZ Agility 3 SSD (SandForce SF-2281)

Problems were reported testing Groundhog with the OCZ Agility 3 SSD. The identify command works but for read and write commands the FPGA does not respond.

Id #908 | Release: None | Updated: Dec 12, 2013 at 1:10 PM by Kusanagi2012 | Created: Dec 12, 2013 at 12:42 PM by Kusanagi2012

48-bit LBA addressing

48-bit LBA addressing is hard-coded in the Verilog source code of Groundhog. Some devices may only support legacy 28-bit addressing, e.g., the OCZ core series V2 SSD (Controller: JMicron JMF602B) ...

Id #904 | Release: None | Updated: Dec 5, 2013 at 9:26 AM by Kusanagi2012 | Created: Dec 5, 2013 at 9:26 AM by Kusanagi2012

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